Cadence Design Systems has announced the availability of 56G long-reach SerDes IP on TSMC’s N7 and N6 process technologies. Hyperscale computing continues to be the main driver for very high-speed SerDes, and 112G/56G is a key enabler for cloud data centre and optical networking applications.
56G connectivity is particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems. To address this broader market, Cadence has expanded its PAM4 SerDes portfolio with 56G long-reach SerDes IP on the TSMC N7 and N6 processes delivering optimized power, performance and area (PPA).
Cadence is ready to engage with customers immediately on 5G, compute server processor and machine learning workload-accelerator system-on-chip (SoC) design enablement. The Cadence® 56G long-reach SerDes IP delivers design excellence in support of the Cadence Intelligent System Design™ strategy, offering designers a number of benefits, including:
- 36db+ insertion loss using Cadence’s well-proven multi-rate DSP technology.
- Industrial temperature range, CPRI data rate support and per-lane PLL are ideal for 5G applications.
- 56G long-reach performance has been achieved on N7 test silicon and is compatible with the N6 process.
- Fully compliant with the IEEE standard specification.
- Programmable power configurations via a unique firmware-controlled adaptive power optimizer, which provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements.
- Optimal data recovery through the programmable DSP-based architecture, which allows optimal power delivery for a given reach and provides superior data recovery under lossy and noisy channel conditions.
- Improved flexibility enabled by the extended reach capability lets customers use lower cost PCBs and achieve greater flexibility in PCB and system design
“We are pleased to see Cadence expand its PAM4 offerings to include 56G and extend support to TSMC N7 and N6 process technologies,” said Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. “This joint effort combining Cadence’s leading edge SerDes IP and TSMC’s advanced process technologies will help our customers unleash their silicon innovations for emerging 5G and hyperscale data center applications.”
Rishi Chugh, Vice President of Product Marketing, IP Group at Cadence, added: “After being first to market in 2019 with silicon-proven 112G-LR SerDes on TSMC 7nm technology, we have now expanded our offering to include PPA-optimized 56G-LR to address the connectivity needs of the 5G infrastructure and AI/ML market. This new PAM4-based 56G-LR SerDes is based on Cadence’s well-proven multi-rate DSP technology.
“The availability of Cadence’s 56G long-reach SerDes IP on the TSMC N7 and N6 processes accelerates the adoption and deployment of cost-effective 100G and 400G networks.”
