Cadence Design Systems has announced the availability of the industry’s first Verification IP (VIP) in support of the new DisplayPort 2.0 standard. The Cadence VIP for DisplayPort 2.0 enables designers to quickly and thoroughly complete the functional verification of their mobile, Audio-Visual and AR/VR system-on-chip (SoC) designs with less effort and greater assurance that the design will operate as expected.
The latest Cadence VIP for DisplayPort 2.0 has been architected to meet the specifications of the new standard—enhancing design verification productivity, ensuring high-quality designs and delivering maximum performance. The Cadence VIP for DisplayPort 2.0 offers the industry’s most comprehensive protocol validation solution for DisplayPort designs and includes a configurable bus functional model (BFM), a protocol monitor and a library of integrated protocol checks to optimize verification predictability.
Additionally, the VIP has been designed for easy integration into testbenches at IP, SoC and system levels, helping engineers reduce time to first test and accelerate verification closure.
Maurizio Paganini, EVP and COO at MegaChips, a highly innovative fabless semiconductor company in Japan, and a leading developer of semiconductors with expertise in analog, digital and MEMS technology, said: “Our team has successfully utilized the Cadence VIP for DisplayPort for previous versions of the specification, which enabled us to deliver advanced audio and video IP solutions for personal computing, mobile and consumer AV devices.
“We are happy to see Cadence deliver VIP for the DisplayPort 2.0 specification. The DisplayPort 2.0 specification will be supported in our next generation of products for mobile computing, enterprise connectivity, gaming, AR/VR and AV streaming systems.”
Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence, said: “By releasing the first-to-market VIP for DisplayPort 2.0, we’re enabling early adopters to ensure their designs comply with the specification while achieving the fastest path to IP verification closure.
“We have been working closely with early adopters of the spec, which has enabled us to provide a solid and high-quality verification IP for advanced designs for automotive, mobile and machine learning applications.”
The Cadence Verification IP portfolio, including the latest VIP for DisplayPort 2.0, is part of the broader Cadence Verification Suite and is optimized for Xcelium Parallel Logic Simulation, along with supported third-party simulators. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.
The Cadence Verification IP supports the company’s Intelligent System Design strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.
