The availability of the PrimeYield solution, a pre-silicon design yield analysis enabled by patented fast statistical methods and accelerated with advanced machine learning technology, has been announced by Synopsys.
It delivers design yield analysis and optimization over one thousand times faster than existing solutions and is scalable to volume production system-on-chips (SoCs) with billions of transistors, enabling SoC designers to shift-left design yield optimization to pre-silicon design phases.
“The ability to identify and fix yield hotspots during the pre-silicon design phase is a game-changer,” said Dan Hutcheson, Chief Executive Officer and Chairman at VLSI Research. “Shifting-left design yield optimization before trial production without the need for a full Monte Carlo statistical simulation significantly lowers non-recurring engineering cost, improves productivity, and, more importantly, shortens the time-to-money for a new design.”
PrimeYield’s innovative fast statistical engine uniquely leverages the core engines of Synopsys’ gold-standard PrimeTime signoff and HSPICE simulation tools and overcomes the turnaround time challenges that previously prohibited full statistical pre-silicon yield analysis with machine learning technologies, enabling pre-silicon design yield analysis and optimization for every design of any size.
With the addition of yield as a fourth design quality metric, now PPA-Y (power, performance, area, and yield), the Synopsys Fusion Design Platform can deliver silicon designs that are faster, lower power, and the most cost effective.
Accelerated by machine learning technology, PrimeYield performs fast Monte Carlo statistical simulation on critical timing paths with true HSPICE accuracy within minutes, versus the days or weeks required by full statistical simulations.
Its patented parametric yield analysis with statistical correlation modeling enables true statistical-based yield analysis and optimization on large-scale SoCs with billions of cells, an analysis previously feasible only for a few dozen cells.
PrimeYield can rapidly identify and drive optimization of yield-impacting cells caused by statistical correlation and sensitivity to various design variations, such as supply voltage drops or manufacturing variability, while using industry standard inputs for immediate deployment.
Jacob Avidan, Senior Vice President of Engineering in Synopsys’ Design Group, said: “Synopsys has a long history of close customer collaborations to drive technology innovations for the growing challenges of SoC design. The introduction of PrimeYield represents a novel approach to yield analysis delivering a shift-left in design yield optimization and lowering manufacturing overhead.”
With the introduction of PrimeYield, Synopsys expands its strong leadership in semiconductor yield analysis from Yield Explorer post-silicon yield analysis and management to pre-silicon statistical yield analysis and optimization, delivering solutions that accelerate predictable customer success.
