Synopsys has announced it has delivered silicon-proven HBM2E PHY IP operating at 3.2Gbps, addressing high throughput requirements of advanced graphics, high-performance computing and networking SoCs. Verified on TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology, Synopsys’ DesignWare HBM2E PHY IP offers a micro-bump array that adheres to the JEDEC HBM2E SDRAM standard for the shortest possible 2.5D package routes and highest signal integrity.
With an aggregated bandwidth of 409 gigabytes per second, the HBM2E PHY delivers the required massive compute performance of system-on-chips (SoCs) in advanced FinFET processes. The HBM2E IP is part of Synopsys’ comprehensive memory interface IP solution that includes DDR5/4/3/2 and LPDDR5/4/3/2 IP, which have been validated in hundreds of designs and shipped in millions of SoCs.
“As a leading global semiconductor manufacturer, SK hynix makes significant investments in developing robust DRAMs that offer increased capacity and processing speed while maintaining strict quality control,” said Jun Hyun Chun, Senior Vice President, HBM Product Champion and Head of DRAM Design at SK hynix. “We continue to collaborate with Synopsys to provide customers with a high-performance HBM DRAM solution that is fully-tested and interoperable with Synopsys’ DesignWare HBM2E IP, which delivers the required capacity, throughput and power of compute-intensive SoCs in advanced processes.”
“TSMC’s long history of successful collaboration with Synopsys has provided our mutual customers with access to a broad portfolio of high-quality DesignWare IP on TSMC’s advanced process technologies, which they can integrate into their high-performance SoCs for a wide range of applications,” added Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. “TSMC’s industry-leading N7 process and CoWoS packaging technologies combined with Synopsys’ silicon-proven DesignWare HBM2E IP allows designers to achieve faster silicon-to-package manufacturing with improved yield, while minimizing integration risk.”
“High-performance computing SoCs are requiring significantly more memory bandwidth to manage the massive amounts of data transfer to support rich graphics and machine learning workloads,” said John Koeter, Senior Vice President of Marketing and Strategy for IP at Synopsys. “As the leading memory interface IP provider, Synopsys delivers a range of silicon-proven DesignWare Memory Interface IP solutions with leading power, performance, and area to address the most challenging throughput requirements.”
