Synopsys has announced its expanded collaboration with Broadcom for the creation of semiconductor solutions using Synopsys’ Fusion Design Platform to address a host of design challenges at 7nm and beyond.
Building upon multiple successful 7nm designs, Synopsys and Broadcom are expanding the collaboration to include the creation of 5nm designs based on Synopsys’ Fusion Design Platform. By encompassing tools, flows and methodologies from Synopsys, this collaboration has enabled Broadcom to extract maximum benefits from the latest silicon-process offerings and efficiently deliver value to its customers.
“We are excited with our expanded collaboration with Synopsys on 7nm and 5nm designs and look forward to continuing the combined efforts to deliver high-volume production designs leveraging Synopsys’ Fusion Design Platform,” said Yuan Xing Lee, vice president and head, Central Engineering at Broadcom Inc. “As a global infrastructure technology leader, Broadcom is continually striving for excellence and innovation providing highly differentiated products that enable our customers to excel in their respective markets.”
Synopsys’ Fusion Design Platform is architected to enable design teams to achieve the optimal levels of power, performance and area (PPA) in the most convergent manner possible to ensure the fastest and most predictable time-to-results (TTR). Spanning test-insertion and optimization, RTL synthesis, place and route and design closure-and-signoff, the Synopsys Fusion Design Platform offers a highly converged solution that enables new levels in predictable PPA to address the challenges inherent across the industry’s most advanced designs.
“Close partnerships and collaborations are paramount to ensuring our customers are able to extract maximum entitlement and value from the latest silicon processes,” said Sassine Ghazi, general manager of the Design Group at Synopsys. “Our long-standing relationship with Broadcom, our shared vison of success and our timely execution on the delivery of differentiated value ensure that we continue to deliver together on best-in-class technology.”
Key features include:
- Fusion Compiler RTL-to-GDSII Solution: Highly optimized full-flow support that delivers optimum design routability and convergence coupled to fastest TTR.
- IC Compiler II place-and-route: EUV single-exposure-based routing with optimized 5LPE design rule support, single fin variant-aware legalization, and via stapling to ensure maximum utilization while minimizing dynamic power.
- Design Compiler NXT RTL synthesis: Correlation, congestion reduction, pin access-aware optimization, 5LPE design rule support, and physical guidance for IC Compiler II.
- PrimeTime timing signoff: Near-threshold ultra-low voltage variation modeling, via variation modeling, and placement rule-aware engineering change order (ECO) guidance.
- StarRC parasitic extraction: EUV single pattern-based routing support, and new extraction technologies, such as coverage-based via resistance and vertical gate resistance modeling.
