It has been announced by Cadence Design Systems that TSMC certified Cadence’s design solutions for the new TSMC System-on-Integrated-Chips (TSMC-SoIC) 3D advanced chip stacking technology, which integrates heterogenous chips, including logic ICs and memory, that are fabricated on different process nodes onto a single chip stack for a subsequent packaging process.
A full suite of Cadence digital and signoff, custom/analog, and IC package and PCB analysis tools have been optimized for TSMC’s SoIC chip stacking technology, enabling mutual customers that require heterogenous chipset integration capabilities to create complex designs more efficiently.
SoIC, TSMC’s innovative multi-chip stacking techniques, expands upon TSMC’s 3D Wafer-on-Wafer (WoW) and Chip-on-Wafer (CoW) technologies and address the diverse design requirements for emerging applications, including 5G, AI, IoT and automotive applications.
TSMC and Cadence collaborated to enhance tools, methodologies and flows, supporting mutual customers to manage the overall connectivity and verification of their chip integration solutions as part of the overall design. The entire design cycle is enabled with multiple 3D featured tools working together.
The Cadence tools in the flow include the Innovus Implementation System, Quantus Extraction Solution, Voltus IC Power Integrity Solution, Tempus Timing Signoff Solution, Physical Verification System (PVS), Virtuoso custom IC design platform, SiP Layout, OrbitIO interconnect designer, Sigrity PowerSI 3D EM Extraction Option, Sigrity PowerDC technology, Sigrity XcitePI Extraction, Sigrity XtractIM technology and Sigrity SystemSI technology.
“Cadence and TSMC have a rich history of collaboration, which continues as we today deliver innovative capabilities to support the new advanced TSMC-SoIC chip stacking technology,” said Tom Beckley, Senior Vice President and General Manager, Custom IC & PCB Group at Cadence. “The SoIC solution empowers our mutual customers to employ the latest 3D techniques using our optimized tools, flows and methodologies to meet tight design delivery deadlines.”
Suk Lee, TSMC Senior Director, Design Infrastructure Management Division, added: “The Cadence tools, reference flows and methodologies for our new SoIC advanced chip stacking technology complement our well-established InFO, WoW and CoWoS chip integration solutions, providing customers with even more flexibility to integrate multiple die onto a single device using 3D stacking techniques.
“Our ongoing collaboration with Cadence on advanced packaging technologies has resulted in helping our mutual customers to achieve efficient and successful product designs targeting 5G, AI, IoT and automotive applications.”
