TSMC Unveils 1.6nm Process Technology
TSMC just announced its 1.6nm-class process technology today, an A16 manufacturing process that is the company’s first Angstrom-class production node. Expectations are that it will outperform its predecessor, N2P, significantly.
The company’s 1.6nm-class fabrication process relies on gate-all-around (GAA) nanosheet transistors; however, TSMC uses backside power delivery called Super Power Rail (SPR). Transistor and BSPDN advances are behind tangible performance and efficiency improvements compared to TSMC’s N2P. Based on the design, the node will deliver up to 10% higher clock rate at the same voltage, 15%–20% lower power consumption, and potentially 7%–10% higher transistor density.
Most important is the Super Power Rail backside power delivery network (BSPDN), tailored for AI and HPC processors that have both complex signal wiring and dense power delivery networks. Backside power delivery will be involved with many upcoming process technologies given its performance-increasing transistor density and improved power delivery. TSMC’s technology plugs the backside power delivery network to each transistor’s source and drain using a special contact that also reduces resistance to achieve maximum performance and power efficiency. This BSPDN implementation is more complex than Intel’s Power Via.
Given the resulting expense, the backside power rail implementation is why TSMC did not add this feature to its N2P and N2X process technologies. The company has two distinct non-competing nodes offering a 1.6nm-class node with GAA nanosheet transistors and SPR and 2nm-class nodes with GAAFETs only.
The timeline for A16 is that volume production of A16 will begin in the second half of 2026, with A16-made products available in 2027. This timeline enables A16 to compete with Intel’s 14A node.
